Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Detection of Delay Faults in Memory Address Decoders
Journal of Electronic Testing: Theory and Applications
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Proceedings of the conference on Design, automation and test in Europe
Open Defects in CMOS RAM Address Decoders
IEEE Design & Test
Resistance Characterization for Weak Open Defects
IEEE Design & Test
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Detection of CMOS address decoder open faults with March and pseudo random memory tests
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A highly-efficient transparent online memory test
Proceedings of the IEEE International Test Conference 2001
Testing for resistive opens and stuck opens
Proceedings of the IEEE International Test Conference 2001
March LA: a test for linked memory faults
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Functional Memory Faults: A Formal Notation and a Taxonomy
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Deception by Design: Fooling Ourselves with Gate-level Models
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Tests for Resistive and Capacitive Defects in Address Decoders
ATS '01 Proceedings of the 10th Asian Test Symposium
Defect-Oriented Dynamic Fault Models for Embedded-SRAMs
ETW '03 Proceedings of the 8th IEEE European Test Workshop
Memory Testing Under Different Stress Conditions: An Industrial Evaluation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Test quality analysis and improvement for an embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Test set development for cache memory in modern microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Delay caused by resistive opens in interconnecting lines
Integration, the VLSI Journal
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Intra-gate resistive open defects not only cause sequentialbehaviour in CMOS memory address decoders, but alsolead to delay behaviour. This paper evaluates the faultcoverage of the resistive open defects in the memory addressdecoders. It shows that both the strong and the weak opendefects are not completely covered by applying the well-knownmarch tests and special test pattern sequencespublished in the literature. We demonstrate that the faultcoverage is increased by varying the duty cycle of theinternal clock of the address decoder. For the self-timedmemories, we introduce a simple DFT technique to controlthe duty cycle of the internal clock whichactivates/deactivates the word lines. Using defect-orientedtest, we also created a fault dictionary based on the defectlocation, transistor types, the terminal name and also thefaulty behaviour. The fault dictionary in combination withthe bit-map fail data will facilitate the localization of theopen defects.