New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Memory Testing Under Different Stress Conditions: An Industrial Evaluation
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test
Journal of Electronic Testing: Theory and Applications
Proceedings of the 42nd annual Design Automation Conference
Small-delay defect detection in the presence of process variations
Microelectronics Journal
Ramp Voltage Testing for Detecting Interconnect Open Faults
IEICE - Transactions on Information and Systems
Delay caused by resistive opens in interconnecting lines
Integration, the VLSI Journal
Fault modeling for FinFET circuits
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
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