Resistance Characterization for Weak Open Defects
IEEE Design & Test
The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Testing for resistive opens and stuck opens
Proceedings of the IEEE International Test Conference 2001
Detectability Conditions for Interconnection Open Defects
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Fault Models for Speed Failures Caused by Bridges and Opens
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Defective Behaviours of Resistive Opens in Interconnect Lines
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Voltage- and current-based fault simulation for interconnect open defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Experimental Characterization of CMOS Interconnect Open Defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic generation of analytical models for interconnect capacitances
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clock Faults Induced Min and Max Delay Violations
Journal of Electronic Testing: Theory and Applications
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An accurate electrical fault characterization is required for the correct diagnosis and localization of CMOS interconnect defects. It has been traditionally accepted that a resistive open defect located at the beginning of an interconnecting line causes the maximum possible delay. The first-order approximation is sufficient to model the behaviour of high resistive opens. However, in this paper it is shown that low resistive opens do not follow this behaviour. In these cases, a second-order model is required for a more precise prediction of their defective behaviour, since the maximum delay is obtained for an intermediate location, which depends on the relationship between the open resistance, the on-resistance of the transistor network driving the defective net, the parasitic capacitances and the threshold voltage of the transistors driven by the defective net. For that purpose, an experimental circuit has been designed and fabricated where open defects have been intentionally added in a set of interconnect CMOS lines. Both simulation and experimental results on defective interconnect lines show maximum delays for opens located at intermediate positions provided that the resistance of the open is on the order of the on-resistance of the driving transistor network.