Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Delay caused by resistive opens in interconnecting lines
Integration, the VLSI Journal
Statistical path selection for at-speed test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A number of new transition fault models for resistive vias and contacts in static CMOS circuits that cause speed failures are presented. The uniqueness of the new fault models are formally established. Fault simulation experiments performed on a large microprocessor show that there is no correlation between the newly proposed models and the classical fault models. Finally, we show that failures caused by bridges and opens in domino CMOS circuits require different fault models, and different test application considerations, than static CMOS circuits. It shows that there are defects that do not cause errors when tests are applied at high speed but fail when tests are applied at slow speed. This contradicts an assumption often made in speed-binning.