Proceedings of the 39th annual Design Automation Conference
Resistance Characterization for Weak Open Defects
IEEE Design & Test
On theoretical and practical considerations of path selection for delay fault testing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Finding a Small Set of Longest Testable Paths that Cover Every Gate
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Fault Models for Speed Failures Caused by Bridges and Opens
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
AC Scan Path Selection for Physical Debugging
IEEE Design & Test
A Statistical Fault Coverage Metric for Realistic Path Delay Faults
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
IEEE Design & Test
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
"Victim Gate" Crosstalk Fault Model
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Process and environmental variation impacts on ASIC timing
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
ITC '04 Proceedings of the International Test Conference on International Test Conference
SPEED CLUSTERING OF INTEGRATED CIRCUITS
ITC '04 Proceedings of the International Test Conference on International Test Conference
Criticality computation in parameterized statistical timing
Proceedings of the 43rd annual Design Automation Conference
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Non-Gaussian statistical timing analysis using second-order polynomial fitting
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Transistor-specific delay modeling for SSTA
Proceedings of the conference on Design, automation and test in Europe
Incremental criticality and yield gradients
Proceedings of the conference on Design, automation and test in Europe
Profit aware circuit design under process variations considering speed binning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parametric analysis to determine accurate interconnect extraction corners for design performance
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Statistical multilayer process space coverage for at-speed test
Proceedings of the 46th Annual Design Automation Conference
Critical path selection for delay fault testing based upon a statistical timing model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defect Modeling Using Fault Tuples
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits
Journal of Electronic Testing: Theory and Applications
Order statistics for correlated random variables and its application to at-speed testing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed in contrast to the localized nature of a traditional fault model. Due to parametric variations, different paths can be critical in different parts of the process space, and the union of such paths must be tested to obtain good process space coverage. This paper proposes an integrated at-speed structural testing methodology, and develops a novel branch-and-bound algorithm that elegantly and efficiently solves the hitherto open problem of statistical path tracing. The resulting paths are used for at-speed structural testing. A new test quality metric is proposed, and paths which maximize this metric are selected. After chip timing has been performed, the path selection procedure is extremely efficient. Path selection for a multimillion gate chip design can be completed in a matter of seconds.