SPEED CLUSTERING OF INTEGRATED CIRCUITS

Authors:
Kenneth A. Brand;Erik Volkerink;Edward J. McCluskey;Subhasish Mitra
Affiliations:
Stanford University, Stanford, CA, USA;Stanford University, Stanford, CA, USA;Stanford University, Stanford, CA, USA;Intel Corporation, Folsom, CA, USA
Venue:
ITC '04 Proceedings of the International Test Conference on International Test Conference
Year:
2004

Citing 0
Cited 5

Performance verification of high-performance ASICs using at-speed structural test

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A Production IR-Drop Screen on a Chip

IEEE Design & Test
Empirical Validation of Yield Recovery Using Idle-Cycle Insertion

IEEE Design & Test
Statistical path selection for at-speed test

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adaptive reduction of the frequency search space for multi-vdd digital circuits

Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

Experimental data on 0.18 test chips shows strong evidence of clustering of speeds of neighboring dies on a wafer. This clustering phenomenon is utilized to develop techniques for predicting the speed of a part from the speeds of three or more of its neighbors. On-chip processor monitors are used to further improve the prediction accuracy of these techniques. Experimental data demonstrates both the effectiveness of these prediction schemes and the possibility of applying of them to reduce the cost of speed binning.