Proceedings of the conference on Design, automation and test in Europe
Defect-Oriented Testing and Defective-Part-Level Prediction
IEEE Design & Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
On Efficiently and Reliably Achieving Low Defective Part Levels
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Accurate Bridging Fault Test Pattern Generator
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
13.3 Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Embedded Deterministic Test for Low-Cost Manufacturing Test
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Experimental Evaluation of Scan Tests for Bridges
ITC '02 Proceedings of the 2002 IEEE International Test Conference
On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Fault Models for Speed Failures Caused by Bridges and Opens
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
A Comparison of Bridging Fault Simulation Methods
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Automatic Test Pattern Generation for Resistive Bridging Faults
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor
ITC '04 Proceedings of the International Test Conference on International Test Conference
Voltage- and current-based fault simulation for interconnect open defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiple-detect ATPG based on physical neighborhoods
Proceedings of the 43rd annual Design Automation Conference
Partitioned n-detection test generation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Forward-looking reverse order fault simulation for n-detection test sets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On clustering of undetectable single stuck-at faults and test quality in full-scan circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Defect aware X-filling for low-power scan testing
Proceedings of the Conference on Design, Automation and Test in Europe
Generation of compact test sets with high defect coverage
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits
Journal of Electronic Testing: Theory and Applications
Non-uniform coverage by n-detection test sets
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A method to generate test patterns referred to as defect aware test patterns is proposed. Defect aware test patterns have greater ability to detect un-modeled defects. The proposed method can be used with any test generation procedure to improve the effectiveness of the tests in detecting un-modeled defects. Experimental results on several industrial designs show the effectiveness of defect aware tests. We also propose a measure to estimate the effectiveness of given test sets in detecting un-modeled defects.