Test set compaction algorithms for combinational circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
On static test compaction and test pattern ordering for scan designs
Proceedings of the IEEE International Test Conference 2001
A study of bridging defect probabilities on a Pentium (TM) 4 CPU
Proceedings of the IEEE International Test Conference 2001
Enhanced DO-RE-ME Based Defect Level Prediction Using Defect Site Aggregation-MPG-D
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test vector decomposition-based static compaction algorithms for combinational circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Forming N-detection test sets without test generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Compact test sets for high defect coverage
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Forward-looking fault simulation for improved static compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We extend the concept of forward-looking reverse order fault simulation to n-detection test sets. Forward-looking reverse order fault simulation is an efficient static test compaction process similar to reverse order fault simulation, but with the advantage that it results in test sets that do not contain any unnecessary tests. The application of test compaction procedures to n-detection test sets is important since the test sets are larger than conventional test sets. We demonstrate that forward-looking reverse order fault simulation produces smaller test sets than reverse order fault simulation and measure the quality of the resulting test sets by their bridging fault coverage.