Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On N-Detect Pattern Set Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Physically-aware N-detect test pattern selection
Proceedings of the conference on Design, automation and test in Europe
MERO: A Statistical Approach for Hardware Trojan Detection
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Generation of compact test sets with high defect coverage
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults
Journal of Electronic Testing: Theory and Applications
Automatic test pattern generation for delay defects using timed characteristic functions
Proceedings of the International Conference on Computer-Aided Design
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This paper evaluates N-detect scan ATPG patterns for their impact to test quality through simulation and fallout from production on a Pentium 4 processor using 90nm manufacturing technology. An incremental ATPG flow is used to generate N-detect test patterns. The generated patterns were applied in production with flows to determine overlap in fallout to different tests. The generated N-detect test patterns are then evaluated based on different metrics. The metrics include signal states, bridge fault coverage, stuck-at fault coverage and fault detection profile. The correlation between the different metrics is studied. Data from production fallout shows the effectiveness of N-detect tests. Further, the correlation between fallout data and the different metrics is analyzed.