IEEE Spectrum
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Tamper Resistance Mechanisms for Secure, Embedded Systems
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A Measure of Quality for n-Detection Test Sets
IEEE Transactions on Computers
Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor
ITC '04 Proceedings of the International Test Conference on International Test Conference
Trojan Detection using IC Fingerprinting
SP '07 Proceedings of the 2007 IEEE Symposium on Security and Privacy
Towards trojan-free trusted ICs: problem analysis and detection scheme
Proceedings of the conference on Design, automation and test in Europe
Power supply signal calibration techniques for improving detection resolution to hardware Trojans
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A region based approach for the identification of hardware Trojans
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
On-demand transparency for improving hardware Trojan detectability
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Hardware Trojan detection using path delay fingerprint
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
IEEE Spectrum
Combining multiple DFT schemes with test generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Self-referencing: a scalable side-channel approach for hardware Trojan detection
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Hardware Trojan side-channels based on physical unclonable functions
WISTP'11 Proceedings of the 5th IFIP WG 11.2 international conference on Information security theory and practice: security and privacy of mobile devices in wireless communication
Hardware trojan design and detection: a practical evaluation
Proceedings of the Workshop on Embedded Systems Security
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In order to ensure trusted in---field operation of integrated circuits, it is important to develop efficient low---cost techniques to detect malicious tampering (also referred to as Hardware Trojan ) that causes undesired change in functional behavior. Conventional post--- manufacturing testing, test generation algorithms and test coverage metrics cannot be readily extended to hardware Trojan detection. In this paper, we propose a test pattern generation technique based on multiple excitation of rare logic conditions at internal nodes. Such a statistical approach maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation. Moreover, the proposed test generation approach can be effective towards increasing the sensitivity of Trojan detection in existing side---channel approaches that monitor the impact of a Trojan circuit on power or current signature. Simulation results for a set of ISCAS benchmarks show that the proposed test generation approach can achieve comparable or better Trojan detection coverage with about 85% reduction in test length on average over random patterns.