Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Interconnect parasitic extraction in the digital IC design methodology
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A virtual 3-D fast extractor for interconnect capacitance of multiple dielectrics
Microelectronic Engineering
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT
Journal of VLSI Signal Processing Systems
Modeling the Frequency-Dependent Parameters of High-Speed Interconnects: A Neural Network Approach
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
Interconnect capacitance extraction for system LCD circuits
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Delay caused by resistive opens in interconnecting lines
Integration, the VLSI Journal
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An analytical-model generator for interconnect capacitances is presented. It obtains analytical expressions of self and coupling capacitances of interconnects for commonly encountered configurations, based on a series of numerical simulations and a partial knowledge of the flux components associated with the configurations. The configurations which are currently considered by this model generator are: (a) single line; (b) crossing lines; (c) parallel lines on the same layer; and (d) parallel lines on different layers (both overlapping and nonoverlapping)