Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Critical path minimization using retiming and algebraic speed-up
DAC '93 Proceedings of the 30th international Design Automation Conference
Simultaneous driver and wire sizing for performance and power optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Architectural power analysis: the dual bit type method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Investigation into micropipeline latch design styles
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Memory segmentation to exploit sleep mode operation
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Logic extraction and factorization for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Feedback, correlation, and delay concerns in the power estimation of VLSI circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Issues in low-power design for telecom
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Early power exploration—a World Wide Web application
DAC '96 Proceedings of the 33rd annual Design Automation Conference
VLSI implementation of discrete wavelet transform
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Retiming sequential circuits for low power
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Tools and methodologies for low power design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Power optimization of variable voltage core-based systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
A methodology for guided behavioral-level optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Optimized rapid prototyping for real-time embedded heterogeneous multiprocessors
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
McPOWER: a Monte Carlo approach to power estimation
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Delay and bus current evaluation in CMOS logic circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Power estimation tool for sub-micron CMOS VLSI circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Dynamic power management for non-stationary service requests
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Common-case computation: a high-level technique for power and performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A low power hardware/software partitioning approach for core-based embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low-power behavioral synthesis optimization using multiple precision arithmetic
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
High-Level Power Analysis and Optimization
High-Level Power Analysis and Optimization
Power Aware Design Methodologies
Power Aware Design Methodologies
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
An Integrated CAD Environment for Low-Power Design
IEEE Design & Test
Improving CMOS Speed at Low Supply Voltages
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Gate Sizing: A General Purpose Optimization Approach
EDTC '96 Proceedings of the 1996 European conference on Design and Test
How to Transform an Architectural Synthesis Tool for Low Power VLSI Designs
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimizing power using transformations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic generation of analytical models for interconnect capacitances
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In modern VLSI circuits, power consumption has become a design criteria as well as speed and silicon area or gate count. To guide the designer implementing complex applications with real time constraint on dedicated circuits, we present a High Level Synthesis methodology that provides a Register Transfer Level description of an ASIC, from a behavioral description of an algorithm; this complete methodology uses basic techniques such as selection, assignment or scheduling specified for power optimization, associated with a new approach based on data format optimization. Actually, instead of the usual 32-bit floating-point format, it is power efficient to use a fixed-point format provided overflow and computation noise problems are solved. The application of our method on an usual DSP example (the DWT) shows a power reduction of more than 60%.