Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI Architectures

Authors:
S. Gailhard;N. Julien;A. Baganne;E. Martin
Affiliations:
-;-;-;-
Venue:
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Year:
1999

Citing 0
Cited 1

Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT

Journal of VLSI Signal Processing Systems

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Abstract

The acoustic echo cancellation with adaptive filters is a computationally intensive problem that needs real time cost effective solutions for embedded systems. Low Power optimized signal processing architectures are likely to provide such solutions in the future. In this paper, we present different real-time optimized architectures of the popular Gmdf a algorithm, obtained by a HLS CAD tool providing trade-off between area and power dissipation.