A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance

Authors:
Zhaozhi Yang;Zeyi Wang;Shuzhou Fang
Affiliations:
Dept. of Computer Science and Technology, Tsinghua University, Beijing 100084, China;Dept. of Computer Science and Technology, Tsinghua University, Beijing 100084, China;Dept. of Computer Science and Technology, Tsinghua University, Beijing 100084, China
Venue:
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Year:
2001

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Abstract

A virtual 3-D extractor of the single dielectric is presented in this paper. In the indirect boundary integral equations, the plane charge distribution on the surface of conductors is replaced with mesh charge distribution, and we use the multipole-accelerated algorithm to further depress the computational complexity. Numerical results show that its computational complexity is about O(n), where n is the number of the discrete variables. Within the comparable accuracy, it runs several times faster than the Fastcap, which is a very advanced multipole-accelerated parasitic capacitance extractor now.