Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology

Authors:
Jason Cong;Lei He;Andrew B. Kahng;David Noice;Nagesh Shirali;Steve H.-C. Yen
Affiliations:
UCLA, Computer Science Dept., Los Angeles, CA;UCLA, Computer Science Dept., Los Angeles, CA;Cadence Design Systems, Inc., San Jose, CA;Cadence Design Systems, Inc., San Jose, CA;Cadence Design Systems, Inc., San Jose, CA;Cadence Design Systems, Inc., San Jose, CA
Venue:
DAC '97 Proceedings of the 34th annual Design Automation Conference
Year:
1997

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Abstract

This paper addresses post-routing capacitance extraction duringperformance-driven layout.We first show how basic driversin process technology (planarization and minimum metal densityrequirements) actually simplify the extraction problem; wedo this by proposing and validating five "foundations" throughdetailed experiments with representative 0.18驴m process parametersand a 3-D field solver.We then present a simple yetaccurate 2 1/2-D extraction methodology directly based on thefoundations.This methodology has been productized and isbeing shipped with the Cadence Silicon Ensemble 5.0 product.We conclude that the 2 1/2-D approach has sufficient accuracyfor current and near-term process generations.