GMRES: a generalized minimal residual algorithm for solving nonsymmetric linear systems
SIAM Journal on Scientific and Statistical Computing
A fast algorithm for particle simulations
Journal of Computational Physics
Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Chip parasitic extraction and signal integrity verification (extended abstract)
DAC '97 Proceedings of the 34th annual Design Automation Conference
A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Modeling and extraction of interconnect capacitances for multilayer VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Parallel Multipole Accelerated 3-D Capacitance Simulator Based on an Improved Model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic generation of analytical models for interconnect capacitances
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
New multipole method for 3-D capacitance extraction
Journal of Computer Science and Technology
| Hi-index | 2.88 |
As features in VLSI reach submicron sizes, the parasitic interconnect must be calculated even more quickly and accurately. In this paper, we present a virtual 3-D extractor of multiple dielectrics that is very fast. In the indirect boundary integral equations from classical potential theory, we replaced the plane charge distribution on the surfaces of conductors with metal mesh charge distribution to simplify the 3-D structure. We also adopted the multipole acceleration with improved non-uniform cube partitioning to further simplify the computational complexity. Numerical results show that the computational complexity of our algorithm is about O(n).