Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Hierarchical 2-D field solution for capacitance extraction for VLSI interconnect modeling
DAC '97 Proceedings of the 34th annual Design Automation Conference
A fast hierarchical algorithm for 3-D capacitance extraction
DAC '98 Proceedings of the 35th annual Design Automation Conference
Boundary element method macromodels for 2-D hierachical capacitance extraction
DAC '98 Proceedings of the 35th annual Design Automation Conference
Modeling and extraction of interconnect capacitances for multilayer VLSI circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automatic generation of analytical models for interconnect capacitances
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Fast and accurate interconnect parasitic parameter extraction has become increasingly critical for verification and analysis in VLSI today. In this paper, a fast hierarchical extraction approach based on Boundary Element Method (BEM) is presented for 3-D parasitic capacitance computation. Hierarchical partition of the 3-D field creates many parts which are called 3-D BEM blocks. After combining all the 3-D BEM blocks, the capacitance matrix for a given set of nets can be computed by applying the boundary conditions. Numerical results shows that this method performs many times faster than the 3-D field solver, with equal accuracy.