Detectability Conditions of Full Opens in the Interconnections
Journal of Electronic Testing: Theory and Applications
On tests to detect via opens in digital CMOS circuits
Proceedings of the 45th annual Design Automation Conference
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines
Journal of Electronic Testing: Theory and Applications
Ramp Voltage Testing for Detecting Interconnect Open Faults
IEICE - Transactions on Information and Systems
Partitioned n-detection test generation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Delay caused by resistive opens in interconnecting lines
Integration, the VLSI Journal
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The detectability of interconnection opens by logic and IDDQ testing is investigated. Opens in interconnection paths disconnect the driven gate(s) from the driving gate. An electrical model for interconnection opens is used to predict the detectability of this type of opens. Using the proposed model, explicit analytical expressions have been obtained to determine the conditions for reliable detection of this defect by logic and IDDQ testing.The cases of full controllability and non-full controllability of the signals at the coupling lines have been analyzed. The effect of the trapped charge during fabrication has also been investigated. In addition, it has been found that the detectability of interconnection opens depends on the metal level where the signals are laid-out. The detectability dependency of interconnection opens on the test generation process has been analyzed.