Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Fault simulation of interconnect opens in digital CMOS circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
IEEE Design & Test
IC Reliability and Test: What Will Deep Submicron Bring?
IEEE Design & Test
Residual Charge on the Faulty Floating Gate MOS Transistor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Defect Classes - An Overdue Paradigm for CMOS IC
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
IDDQ Testing of CMOS Opens: An Experimental Study
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Incorporating Physical Design-for-Test into Routing
Proceedings of the IEEE International Test Conference
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An unexpected factor in testing for CMOS opens: the die surface
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Detectability Conditions for Interconnection Open Defects
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Defect-Based Delay Testing of Resistive Vias-Contacts A Critical Evaluation
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Optimal Conditions for Boolean and Current Detection of Floating Gate Faults
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Charge-based fault simulation for CMOS network breaks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines
Journal of Electronic Testing: Theory and Applications
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Opens in interconnection paths disconnect the driven gate(s) from the driving gate. Detectability conditions to test full opens in interconnections are investigated. It has been found that the detectability of this defect depends strongly on the signals at the driving gate and coupling lines. Three possible situations are analyzed. The first is when there is full controllability of both the signal driving the open and the signal(s) at the coupling line(s). Then, the cases of partial and low controllability of the signals are analyzed. Conditions for reliable detection of this defect by logic and IDDQ testing have been determined. In addition, it has been found that the detectability of interconnection opens depends on the metal level where the signals are laid-out. Routing design for testability techniques are recommended for some interconnection opens non detectable by either a stuck-at based or IDDQ testing. Experimental data on intentionally designed defective circuit is presented.