The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits

On-chip transient current monitor for testing of low-voltage CMOS IC

DATE '99 Proceedings of the conference on Design, automation and test in Europe

Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs

Proceedings of the conference on Design, automation and test in Europe

Detectability Conditions of Full Opens in the Interconnections

Journal of Electronic Testing: Theory and Applications

Resistance Characterization for Weak Open Defects

IEEE Design & Test

Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs

IEEE Transactions on Computers

Testing for Tunneling Opens

ITC '00 Proceedings of the 2000 IEEE International Test Conference

Simulation Based Analysis of Temperature Effect on the Faulty Behavior of Embedded DRAMs

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Testing for Resistive Opens and Stuck Opens

ITC '01 Proceedings of the 2001 IEEE International Test Conference

Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Test Strategy Sensitivity to Defect Parameters

ITC '97 Proceedings of the 1997 IEEE International Test Conference

Optimal Conditions for Boolean and Current Detection of Floating Gate Faults

ITC '99 Proceedings of the 1999 IEEE International Test Conference

Estimating detection probability of interconnect opens using stuck-at tests

Proceedings of the 14th ACM Great Lakes symposium on VLSI

Detection probabilities of interconnect breaks: an analysis

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI

A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines

Journal of Electronic Testing: Theory and Applications

Delay caused by resistive opens in interconnecting lines

Integration, the VLSI Journal

Detection probabilities of interconnect breaks: an analysis

Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI

Criteria for static current estimation: how good are they? an approach incorporating IC quality requirements

SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design

Defect classes - an overdue paradigm for CMOS IC testing

ITC'94 Proceedings of the 1994 international conference on Test

Residual charge on the faulty floating gate MOS transistor

ITC'94 Proceedings of the 1994 international conference on Test

Variable supply voltage testing for analogue CMOS and bipolar circuits

ITC'94 Proceedings of the 1994 international conference on Test

System-level impact of chip-level failure mechanisms and screens

Proceedings of the International Conference on Computer-Aided Design