Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Industrial evaluation of DRAM tests
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Proceedings of the conference on Design, automation and test in Europe
The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
How we test Siemens Embedded DRAM Cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
March LA: a test for linked memory faults
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Synchronous Dynamic Memory Test Construction: A Field Approach
MTDT '00 Proceedings of the 2000 IEEE International Workshop on Memory Technology, Design and Testing
Functional Memory Faults: A Formal Notation and a Taxonomy
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
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Temperature has proven to be an effectivestress condition, commonly used to stress memory devicesand to detect special types of failure mechanisms. In thispaper, a new approach is presented where temperature isused as a test parameter to increase the fault coverageof specific tests. This is done using defect injection andsimulation of a memory model at different temperatures.The analysis presents new types of detection conditions formemories and evaluates the impact of temperature on theseconditions.