Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
Proceedings of the conference on Design, automation and test in Europe
Simulation Based Analysis of Temperature Effect on the Faulty Behavior of Embedded DRAMs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test and Repair of Large Embedded DRAMs: Part 1
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Test and Repair of Large Embedded DRAMs: part 2
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering
IBM Journal of Research and Development
SoC Design and Test Considerations
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Space of DRAM fault models and corresponding testing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Embedded DRAM: technology platform for the Blue Gene/L chip
IBM Journal of Research and Development
Alternate hammering test for application-specific DRAMs and an industrial case study
Proceedings of the 49th Annual Design Automation Conference
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The techniques used to test Siemens EmbeddedDRAM Cores are described. Test Isolation and Design-For-Test logic is built in to the core interface, while externalaccess and Algorithmic Pattern Generation are handledby a central Test Controller. All tests used forstandard DRAM's can be applied to the DRAM cores, butonly a subset of these are used for any given product.