Defect Classes - An Overdue Paradigm for CMOS IC
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
On n-detection test sequences for synchronous sequential circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
An Accurate Interconnection Length Estimation for Computer Logic
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Introduction to Probability Models, Ninth Edition
Introduction to Probability Models, Ninth Edition
Detection probabilities of interconnect breaks: an analysis
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines
Journal of Electronic Testing: Theory and Applications
Ramp Voltage Testing for Detecting Interconnect Open Faults
IEICE - Transactions on Information and Systems
Detection probabilities of interconnect breaks: an analysis
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
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An interconnect break is a break that occurs in the interconnect wiring, which results in logic gate inputs being disconnected from the drivers and causes the wire to float. Interconnect breaks are the most common types of breaks in modern $CMOS$ integrated circuits, so testing and detecting these breaks has become very important. This paper proposes a model by which standard tests for stuck-at-faults can be used to detect interconnect breaks in a circuit. We do a worst-case analysis of the detection of these breaks and calculate the minimum number of test vectors required to detect breaks with a specified confidence level, using n-detection principles. To enhance the understanding of the breaks in the circuit, we present a statistical model based on the length distribution of the wires surrounding the floating wire where the break occurs. From the model we compute the detection probabilities of such breaks and show that the worst case of detection is when the bias voltage is the same as the logic threshold voltage.