On generating compact test sequences for synchronous sequential circuits
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
On static compaction of test sequences for synchronous sequential circuits
DAC '96 Proceedings of the 33rd annual Design Automation Conference
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
On the effects of test compaction on defect coverage
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On the decline of testing efficiency as fault coverage approaches 100%
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip
ITC '98 Proceedings of the 1998 IEEE International Test Conference
6.3 Experimental Results for IDDQ and VLV Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
An Experimental Study of N-Detect Scan ATPG Patterns on a Processor
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Estimating detection probability of interconnect opens using stuck-at tests
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Detection probabilities of interconnect breaks: an analysis
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
A delay fault model for at-speed fault simulation and test generation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Detection probabilities of interconnect breaks: an analysis
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
System-level impact of chip-level failure mechanisms and screens
Proceedings of the International Conference on Computer-Aided Design
Multi-pattern n-detection stuck-at test sets for delay defect coverage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Test sets that detect each stuck-at fault n1 times (called n-detection test sets) were shown to achieve higher defect coverages than conventional single stuck-at 1-detection test sets. Previous studies of n-detection test sets concentrated on combinational circuits. In this work, we study n-detection test sequences for synchronous sequential circuits. We propose four definitions of the number of detections achieved by a test sequence. We describe fault simulation and test generation procedures based on these definitions, and evaluate them on benchmark circuits by using non-feedback bridging faults to model defects. The results indicate the usefulness of the simplest definition in generating test sequences that achieve improved defect coverages.