Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Random Pattern Testing Versus Deterministic Testing of RAMs
IEEE Transactions on Computers
Switch-level testability of the dynamic CMOS PLA
Integration, the VLSI Journal
Boundary-scan design principles for efficient LSSD ASIC testing
IBM Journal of Research and Development
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Theory of Transparent BIST for RAMs
IEEE Transactions on Computers
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Open Defects in CMOS RAM Address Decoders
IEEE Design & Test
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms
IEEE Transactions on Computers
Two-Pattern Test Capabilities of Autonomous TPG Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test and Testability Techniques for Open Defects in RAM Address Decoders
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On the Generation of Pseudo-Deterministic Two-Patterns Test Sequence with LFSRs
EDTC '97 Proceedings of the 1997 European conference on Design and Test
False write through and un-restored write electrical level fault models for SRAMs
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
Integration of Non-Classical Faults in Standard March Tests
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Rambist builder: a methodology for automatic built-in self-test design of embedded rams
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
IEEE Transactions on Computers
IEEE Transactions on Computers
Diagnostic testing of embedded memories using BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Detection of Delay Faults in Memory Address Decoders
Journal of Electronic Testing: Theory and Applications
Integration of Non-Classical Faults in Standard March Tests
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
March iC-: An Improved Version of March C- for ADOFs Detection
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test
Journal of Electronic Testing: Theory and Applications
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions
Journal of Electronic Testing: Theory and Applications
A simple diagnostic method for memory testing
ICECS'03 Proceedings of the 2nd WSEAS International Conference on Electronics, Control and Signal Processing
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A new method to integrate a test for CMOS address decoder open faults into March and pseudo random tests employed for testing semiconductor memories is presented. For commonly used memory organizations, March tests are implemented that, in addition to their original target faults, detect all CMOS address decoder open faults. The detection of these faults has been believed to require separate deterministic test patterns or tests of higher order. Address sequences generated by special Complete LFSRs and address dependent data are utilized to alter March tests to detect all address decoder open faults and retain the detection properties of the original tests. The additional overhead in terms of silicon area for an on-chip realization of a built-in March test with the added fault detection features is negligible, and the test application time remains of 0(N).