Optimal layout to avoid CMOS stuck-open faults
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Reducing the CMOS RAM test complexity with IDDQ and voltage testing
Journal of Electronic Testing: Theory and Applications
Tutorial on semiconductor memory testing
Journal of Electronic Testing: Theory and Applications - Special issue: on memory testing
A New Testing Acceleration Chip for Low-Cost Memory Tests
IEEE Design & Test
Development of Fault Model and Test Algorithms for Embedded DRAMs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Test generation for MOS circuits using D-algorithm
DAC '83 Proceedings of the 20th Design Automation Conference
Detection of CMOS address decoder open faults with March and pseudo random memory tests
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Integration of Non-Classical Faults in Standard March Tests
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
The Implementation of Pseudo-Random Memory Tests on Commercial Memory Testers
ITC '97 Proceedings of the 1997 IEEE International Test Conference
March iC-: An Improved Version of March C- for ADOFs Detection
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test
Journal of Electronic Testing: Theory and Applications
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions
Journal of Electronic Testing: Theory and Applications
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time
Journal of Electronic Testing: Theory and Applications
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It is a prevalent assumption that all RAM address decoder defects can be modelled as RAM array faults influencing one or more RAM cells. Therefore, can be implicitly detected by testing the RAM matrix with the march tests. Recently, we came across some failures in embedded SRAMs which were not detected by the march tests. The carried out analysis demonstrated the presence of open defects in address decoders that can not be modelled as the conventional coupling faults, therefore, are not detected by the march tests. In this article, we present the test and testability strategies for such hard to detect open defects.