The Implementation of Pseudo-Random Memory Tests on Commercial Memory Testers

Authors:
Ad J. van de Goor;Mike Lin
Affiliations:
-;-
Venue:
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Year:
1997

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Abstract

The increasing emphasis on reducing thedefect level of shipped memory parts demands very highfault coverage of memory tests. Deterministic tests havethe advantage of 100% fault coverage for the targeted(i.e., anticipated) faults. However, with each newtechnology, new layout and new fab process, new typesof defects will show up; the probability of occurrence ofthese defects is not known before production start and, inaddition, may vary during the time period the parts areproduced.Pseudo-random (PR) memory tests are tests whichhave the capability to detect any fault (defect) of anymodel; albeit with some probability less than 100%; thefault coverage is modular and depends on the test time,which makes them very attractive. However, problemsarise when commercial testers have to be used forapplying PR tests. This paper illustrates these problemsand shows how they can be overcome. The results areapplicable to a large class of commercial memory testersthereby making them useable for PR memory tests.