A synthesizable ram bist circuit for applying an O(n log/sub 2/ n) test that detects scrambled static pattern-sensitive faults

Authors:
B. F. Cockburn;D. P. Sarda
Affiliations:
-;-
Venue:
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
Year:
1996

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Abstract

Abstract: In this paper we describe improvements and extensions to the BIST RAM scheme described earlier by Cockburn and Sat. The first improvement is the use of maximum transition counters, instead of binary counters or linear feedback shift registers, to generate the addresses that are used in the self-test. This change increases the ability of the tests to detect delay faults in the peripheral circuitry. The second improvement is the extension of the original scheme to use a new O(n log/sub 2/ n) test for detecting scrambled static pattern sensitive faults. The O(n log/sub 2/ n) test is similar to a test described by Franklin and Saluja; however, the new test is approximately 20% shorter. In addition, the new test is transparent; that is, the contents of a fault-free memory are restored by the time the self-test has terminated. The RAM BIST circuit for the new scheme was specified and verified using VHSIC Hardware Description Language (VHDL). Instances of the BIST circuit can be synthesized automatically for any arbitrary RAM size using commercial logic synthesis tools. As with the scheme described by Cockburn and Sat, the hardware area overhead of the new scheme is below 1% for 4 Mb RAMs and this figure drops rapidly for larger RAM sizes.