Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Minimal cost one-dimensional linear hybrid cellular automata of degree through 500
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms
IEEE Transactions on Computers
BIST Generators for Sequential Faults
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Two-Pattern Test Capabilities of Autonomous TPG Circuits
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
DS-LFSR: A New BIST TPG for Low Heat Dissipation
Proceedings of the IEEE International Test Conference
Tree-Structured Linear Cellular Automata and Their Applications as PRPGs
Proceedings of the IEEE International Test Conference
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
IEEE Design & Test
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This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators (TPGs). Bit transition maximization is a heuristic technique that involves increasing the probability that a bit will change values going from one test pattern to the next. For most of the ISCAS-85 benchmarks and many of the ISCAS- 89 benchmarks bit transition maximization enhances the fault coverage of two-pattern faults such as gate delay faults and CMOS transistor stuck-open faults. It achieves these benefits without reducing the fault coverage with respect to classical stuck-at faults.