Fault Diagnosis of RAMs from Random Testing Experiments
IEEE Transactions on Computers
An overview of deterministic functional RAM chip testing
ACM Computing Surveys (CSUR)
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Error catch and analysis for semiconductor memories using march tests
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Using March Tests to Test SRAMs
IEEE Design & Test
Shmoo Plotting: The Black Art of IC Testing
IEEE Design & Test
Detection of CMOS address decoder open faults with March and pseudo random memory tests
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Designing a Memory Module Tester
MTDT '99 Proceedings of the 1999 IEEE International Workshop on Memory Technology, Design, and Testing
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
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We present the efficient and simple diagnostic method for memory integrity test. This paper gives an introduction how to construct memory tests and test flows. A typical memory test steps through the memory array and tests all cells. It ensures that addresses works and all cells can store and retrieve '0' and '1' information. Step by step a basic test is developed choosing a pattern. Starting with this basic pattern, modifications for characterization, diagnostic are discussed. These variations are then used to construct a test sequence to ensure functionality according to the data sheet specification. The proposed algorithms facilitate the simple and efficient diagnosis of semiconductor memories.