Diagnostic testing of embedded memories using BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Design and Test of Large Embedded Memories: An Overview
IEEE Design & Test
Detection of CMOS address decoder open faults with March and pseudo random memory tests
ITC '98 Proceedings of the 1998 IEEE International Test Conference
End-to-end register data-flow continuous self-test
Proceedings of the 36th annual international symposium on Computer architecture
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Abstract: In this paper, we report a built-in self-test methodology for embedded RAMs. A CAD tool has been developed to synthesize the BIST circuitry for the compiled RAMs. The blocks such as address generator, pattern generator, multiplexers, state machine, control logic and comparator are automatically synthesized with this tool. The BIST logic is personalized to the RAM configuration and its physical bit map. This provides coverage of all stuck-at, state transition and coupling faults. In multi-port RAMs port-coupling faults are also detected. RAM addresses are generated by the address generator based upon the March algorithm. A set of multiplexers selects the path to the address, data and control lines, either from the RAM (during normal operation), or from the pattern generator (during test mode). The state machine and control logic provide signals for read, write, port selection and start/end. A comparator evaluates the data written during the write cycle against the RAM's output data to generate a pass/fail flag.