Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Theory of Transparent BIST for RAMs
IEEE Transactions on Computers
Improved Yield Models for Fault-Tolerant Memory Chips
IEEE Transactions on Computers
Aliasing Error for a Mask ROM Built-In Self-Test
IEEE Transactions on Computers
Deterministic Self-Test of a High-Speed Embedded Memory and Logic Processor Subsystem
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Structured Design-for-Debug - The SuperSPARCTM II Methodology and Implementation
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
ASIC Test Cost/Strategy Trade-offs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Testability Strategy of the ALPHA AXP 21164 Microprocessor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Exact Aliasing Computation for RAM BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Faulty chip identification in a multi chip module system
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Industrial evaluation of DRAM tests
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Industrial Evaluation of DRAM SIMM Tests
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Industrial Evaluation of Stress Combinations for March Tests applied to SRAMs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An Industrial Evaluation of DRAM Tests
IEEE Design & Test
Test set development for cache memory in modern microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Analyzing 1,000 faulty 1 Mb SRAM chips that were randomly selected from a single manufacture, we found 251 stuck-at cell faults, 5 stuck-at bit-line faults, 1 stuck-at word-line fault, 46 neighborhood-pattern-sensitive faults, and other kinds of faults. Under the condition that I/sub dd/=4.5 I; temperature=70/spl deg/C, and load capacity C/sub L/=30 pF, we detected margin faults in 460 chips. Because the actual fault data for SRAM chips is rarely reported, the data in this manuscript are very useful and should be of practical importance.