Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Industrial evaluation of DRAM tests
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Test Pattern Development and Evaluation for DRAMs with Fault Simulator RAMSIM
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
A 256Meg SDRAM BIST for Disturb Test Application
Proceedings of the IEEE International Test Conference
March LA: a test for linked memory faults
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Experimental fault analysis of 1 Mb SRAM chips
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Industrial Evaluation of Stress Combinations for March Tests applied to SRAMs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing and Characterization of SDRAMs
IEEE Design & Test
A data acquisition methodology for on-chip repair of embedded memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Industrial Evaluation of DRAM Tests
IEEE Design & Test
Memory testing with a RISC microcontroller
Proceedings of the Conference on Design, Automation and Test in Europe
Alternate hammering test for application-specific DRAMs and an industrial case study
Proceedings of the 49th Annual Design Automation Conference
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This paper describes the results of testing 50 single inlinememory modules (SIMMs), each containing 16 16MbitDRAM chips (DUTs); 39 SIMMs failed, and of the 800DUTs, 116 failed. In total 54 different test algorithms havebeen applied, using up to 168 different stress combinationsfor each test. The results show that GAL9R is the best test.Furthermore, it is shown that burst mode tests detect a completelydifferent class of faults as compared with traditionalword mode tests, and that tests with address scrambling enableddetect more faults.