Memory testing with a RISC microcontroller

Authors:
Ad van de Goor;Georgi Gaydadjiev;Said Hamdioui
Affiliations:
ComTex, Gouda, The Netherlands and Delft University of Technology, The Netherlands;Delft University of Technology, The Netherlands;Delft University of Technology, The Netherlands
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2010

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Abstract

Many systems are based on embedded microcontrollers. Applications demand for production and Power-On testing, including memory testing. Because low-end microcontrollers may not have memory BIST, the CPU will be the only resource to perform at least the Power-On tests. This paper shows the problems, solutions and limitations of CPU-based at-speed memory testing, illustrated with examples from the ATMEL RISC microcontroller.