A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Economic Aspects of Memory Built-in Self-Repair
IEEE Design & Test
Memory testing with a RISC microcontroller
Proceedings of the Conference on Design, Automation and Test in Europe
Low-cost self-test techniques for small RAMs in SOCs using enhanced IEEE 1500 test wrappers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper describes a modular design of a wrapper enabling BIST/BISR for small memories operating as register files or FIFOs in high speed applications such as graphics and networking. The wrapper allows for atspeed test at low overhead and enables a simple repair scheme when millions of bits are used in such memories. The wrapper is intended to provide a standardized interface between memory and test controller, and thus work with any BIST controller, and communication between the two is minimized and at a reduced frequency.