On yield, fault distributions, and clustering of particles
IBM Journal of Research and Development
Architectural Yield Optimization for WSI
IEEE Transactions on Computers
Aliasing Error for a Mask ROM Built-In Self-Test
IEEE Transactions on Computers
Experimental fault analysis of 1 Mb SRAM chips
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Improving yield and reliability of chip multiprocessors
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient built-in redundancy analysis for embedded memories with 2-d redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 15.01 |
Several improvements in the method of yield modeling for memory chips with redundancy are described. First, a direct method of translating defect-monitor data to memory-chip fault eliminates the need for yield-model formulas. This makes possible the accurate modeling of the faults that can be fixed with redundant circuits or other fault-tolerance techniques. A second improvement results from the use of separate frequency distributions for different failure mechanisms instead of the multivariate distributions used until now. The yields of array islands with their own redundant word and bit lines are combined using a new yield formula. Examples of the use of this technique for dynamic-random-access-memory (DRAM) chips are given. A simplified pragmatic approximation technique that appears to be in good agreement with experimental data is also discussed.