Functional Testing of Semiconductor Random Access Memories
ACM Computing Surveys (CSUR)
Computer
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Detection oF Pattern-Sensitive Faults in Random-Access Memories
IEEE Transactions on Computers
An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories
IEEE Transactions on Computers
Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories"
IEEE Transactions on Computers
Efficient Algorithms for Testing Semiconductor Random-Access Memories
IEEE Transactions on Computers
A March Test for Functional Faults in Semiconductor Random Access Memories
IEEE Transactions on Computers
Cache RAM inductive fault analysis with fab defect modeling
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Pseudo-exhaustive word-oriented DRAM testing
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Industrial Evaluation of Stress Combinations for March Tests applied to SRAMs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
The Test and Debug Features of the AMD-K7TM Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Design techniques and test methodology for low-power TCAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An efficient fault detection algorithm for NAND flash memory
ACM SIGAPP Applied Computing Review
DEFCAM: A design and evaluation framework for defect-tolerant cache memories
ACM Transactions on Architecture and Code Optimization (TACO)
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Testing Static Random Access Memories (SRAMs) for all possible failures is not feasible. We have to restrict the class of faults to be considered. This restricted class is called a fault model. A fault model for SRAMs is presented based on physical spot defects, which are modeled as local disturbances in the layout of an SRAM. Two linear test algorithms (length 9N and 13N respectively, where N is the number of addresses) are proposed plus a data retention test that cover 100 % of the faults under the fault model. The 13N test algorithm is generally applicable while the 9N algorithm can only be used in SRAMs with combinational R/W logic. A general solution is given for testing word oriented SRAMs. The practical validity of the fault model and the two test algorithms is verified by a large number of actual wafer tests and device failure analysis.