Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
IEEE Transactions on Computers
Testing Memories for Single-Cell Pattern-Sensitive Faults
IEEE Transactions on Computers
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
IEEE Transactions on Computers
A Graph Model for Pattern-Sensitive Faults in Random Access Memories
IEEE Transactions on Computers
A March Test for Functional Faults in Semiconductor Random Access Memories
IEEE Transactions on Computers
Fault modeling and test algorithm development for static random access memories
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Built-in testing of memory using on-chip compact testing scheme
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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With 16K RAM chips already in commercial use and 64K RAM chips being planned, the increasing length of time needed to run test patterns could lead to cost increases that would offset the advantages of the larger devices. For example, many existing tests of the important pattern-sensitive-fault class, such as galloping 0's and 1's,* require a test length proportional to the square of the number of bits in the RAM chip.1-4Clearly, the time consumed by such tests looms as a major component in the overall costs of chip production.