Self-testing of embedded RAMs

Authors:
Zuxi Sun;Laung-Terng Wang
Affiliations:
Center for Reliable Computing, Computer Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA;Center for Reliable Computing, Computer Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA and R/D Department, Daisy Systems Corporat ...
Venue:
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Year:
1984

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Abstract

A design-for-testability method for embedded RAMs is presented. This method combines both selftest and scan techniques. A simple march test pattern is used in self-test to detect all hard failures in the RAMs. A scan technique is used to detect stuck-at and bridging faults in the comparator and data lines, and to diagnose single stuck-at faults in the RAMs. To obtain better fault coverage, a modified pseudo-random pattern generator is used as an address generator. The overhead is very low and the test time is short.