Built-in testing of memory using on-chip compact testing scheme

Authors:
K. Kinoshita;K. K. Saluja
Affiliations:
Dept. of Information & Behavioral Sciences, Faculty of Integrated Arts & Sciences, Hiroshima University, Hiroshima, Japan;Dept. of Electrical & Computer Engineering, University of Newcastle, New South Wales, Australia
Venue:
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Year:
1984

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Abstract

In this paper we study the problem of testing RAM. A new fault model, which encompasses the existing fault models, is proposed. We then propose a scheme of testing faults from the new fault model using built-in testing techniques. We also determine the complexity of the extra hardware required to implement built-in testing. A novel approach using microcoded ROM for implementation of built-in testing is also proposed and its complexity is determined.