Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
IEEE Transactions on Computers
Built in self testing for detection of coupling faults in semiconductor memories
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
Design for Testability A Survey
IEEE Transactions on Computers
Sequential Network Design Using Extra Inputs for Fault Detection
IEEE Transactions on Computers
Testing Memories for Single-Cell Pattern-Sensitive Faults
IEEE Transactions on Computers
Fault Location in a Semiconductor Random-Access Memory Unit
IEEE Transactions on Computers
Efficient Algorithms for Testing Semiconductor Random-Access Memories
IEEE Transactions on Computers
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
IEEE Transactions on Computers
An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories
IEEE Transactions on Computers
A Graph Model for Pattern-Sensitive Faults in Random Access Memories
IEEE Transactions on Computers
A March Test for Functional Faults in Semiconductor Random Access Memories
IEEE Transactions on Computers
Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests
International Journal of Applied Mathematics and Computer Science - Selected Problems of Computer Science and Control
RTRAM: reconfigurable and testable multi-bit RAM design
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Fault modeling and test algorithm development for static random access memories
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Built-in testing of memory using on-chip compact testing scheme
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Analysis of multibackground memory testing techniques
International Journal of Applied Mathematics and Computer Science - Computational Intelligence in Modern Control Systems
Efficient online memory error assessment and circumvention for Linux with RAMpage
International Journal of Critical Computer-Based Systems
| Hi-index | 15.01 |
Some formal models for pattern-sensitive faults (PSF's) in random-access memories are presented. The problem of detecting unrestricted PSF's is that of constructing a checking sequence for the memory. An efficient procedure for constructing such a checking sequence is presented. A local PSF is defined as a PSF where the faulty behavior of a memory cell Cidepends on a fixed group of cell