Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
A Survey of Combinatorial Gray Codes
SIAM Review
March PS(23N) Test for DRAM Pattern-Sensitive Faults
ATS '98 Proceedings of the 7th Asian Test Symposium
Deterministic tests for detecting scrambled pattern-sensitive faults in RAMs
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
Integration of Non-Classical Faults in Standard March Tests
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Diagnostic Testing of Embedded Memories Based on Output Tracing
MTDT '00 Proceedings of the 2000 IEEE International Workshop on Memory Technology, Design and Testing
Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Exploiting an Infrastructure IP to Reduce the Costs of Memory Diagnosis Costs in SoCs
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Address Sequences for March Tests to Detect Pattern Sensitive Faults
DELTA '06 Proceedings of the Third IEEE International Workshop on Electronic Design, Test and Applications
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Detection oF Pattern-Sensitive Faults in Random-Access Memories
IEEE Transactions on Computers
Testing Memories for Single-Cell Pattern-Sensitive Faults
IEEE Transactions on Computers
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
IEEE Transactions on Computers
Optimal Memory Address Seeds for Pattern Sensitive Faults Detection
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of multibackground memory testing techniques
International Journal of Applied Mathematics and Computer Science - Computational Intelligence in Modern Control Systems
Automation and Remote Control
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It is widely known that pattern sensitive faults are the most difficult faults to detect during the RAM testing process. One of the techniques which can be used for effective detection of this kind of faults is the multi-background test technique. According to this technique, multiple-run memory test execution is done. In this case, to achieve a high fault coverage, the structure of the consecutive memory backgrounds and the address sequence are very important. This paper defines requirements which have to be taken into account in the background and address sequence selection process. A set of backgrounds which satisfied those requirements guarantee us to achieve a very high fault coverage for multi-background memory testing.