RTRAM: reconfigurable and testable multi-bit RAM design

Authors:
Dhiraj K. Pradhan;Nirmala R. Kamath
Affiliations:
Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA;Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA
Venue:
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Year:
1988

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Abstract

An easily testable multi-bit RAM design is proposed which provides dynamic reconfigurability for variable wordsize and multiword access. This design is a modification of the single-bit TRAM design proposed earlier. The basic idea in our design is to divide the RAM into modules and interconnect these modules using a binary tree structure. The design is then augmented by a built-in test structure which reduces the problem of testing the RAM to that of testing a single module. The proposed architecture has the potential to achieve faster access than the traditional architecture with a modest increase in area.