Introduction to VLSI Systems
Computer
Detection oF Pattern-Sensitive Faults in Random-Access Memories
IEEE Transactions on Computers
Testing Memories for Single-Cell Pattern-Sensitive Faults
IEEE Transactions on Computers
Efficient Algorithms for Testing Semiconductor Random-Access Memories
IEEE Transactions on Computers
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
IEEE Transactions on Computers
Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
IEEE Transactions on Computers
Built-in testing of memory using on-chip compact testing scheme
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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This correspondence generalizes Hayes' recent ideas for generating an optimal transition write sequence which forms the "backbone" of his algorithm for testing semiconductor RAM's for pattern-sensitive faults. The generalization, presented in graph theoretic terms, involves two sequential steps. The frmst step results in assigning of a "color" to each memory cell. In the second step, each color is defined as a distinct sequence of bits representing the sequence of states assumed by the correspondingly colored cell. The constraints imposed at each step lead to interesting and general problems in graph theory: the standard graph coloring problem in the first step, and a path projection problem from a binary m-cube to a subcube in the second step. Applications to arbitrary k-cell neighborhoods, and particularly to three-cell neighborhoods are shown.