An overview of deterministic functional RAM chip testing
ACM Computing Surveys (CSUR)
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Testing for Coupled Cells in Random-Access Memories
IEEE Transactions on Computers
Deterministic tests for detecting single V-coupling faults in RAMs
Journal of Electronic Testing: Theory and Applications
Transparent Memory Testing for Pattern-Sensitive Faults
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Pseudo-exhaustive word-oriented DRAM testing
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Detection oF Pattern-Sensitive Faults in Random-Access Memories
IEEE Transactions on Computers
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
IEEE Transactions on Computers
Exhaustive Test Pattern Generation with Constant Weight Vectors
IEEE Transactions on Computers
Iterative exhaustive pattern generation for logic testing
IBM Journal of Research and Development
Intersecting codes and independent families
IEEE Transactions on Information Theory
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Abstract: In this work we investigate the problem of detection and location of single and unlinked multiple pattern sensitive faults in bit oriented RAMs and implementation of a built-in self-test (BIST) unit to test RAM chips in an efficient manner. Our fault model covers cross-talks between any k cells in RAMS. We have reduced the problem of memory testing to the problem of the generation of exhaustive back grounds. Exhaustive tests for detecting coupling faults for k up to 6 (which covers Type I neighborhood) and near exhaustive tests for k up to 9 (which covers Type II neighborhood) are constructed. The systematic nature of the tests constructed enables us to use BIST schemes, for RAMs, with low hardware over heads. We implemented the BIST units for a bit-oriented memory of size IM and calculated the hardware overhead in terms of transistors and area.