Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Generation and application of pseudorandom sequences for random testing
Generation and application of pseudorandom sequences for random testing
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
IEEE Spectrum
Deterministic tests for detecting single V-coupling faults in RAMs
Journal of Electronic Testing: Theory and Applications
Using March Tests to Test SRAMs
IEEE Design & Test
COM (Cost Oriented Memory) Testing
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Fault modeling and test algorithm development for static random access memories
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Exhaustive and Near-Exhaustive Memory Testing Techniques and theirBIST Implementations
Journal of Electronic Testing: Theory and Applications
BIST for Embedded Word-Oriented DRAM
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Built in self testing for detection of coupling faults in semiconductor memories
MTDT '96 Proceedings of the 1996 IEEE International Workshop on Memory Technology, Design and Testing (MTDT '96)
Analysis of multibackground memory testing techniques
International Journal of Applied Mathematics and Computer Science - Computational Intelligence in Modern Control Systems
Journal of Electronic Testing: Theory and Applications
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This paper presents a new methodology for RAM testing based on the PS(n,k) q-ary fault model (q=2/sup w/) which includes most classical fault models for SRAMs and DRAMs. According to this fault model, the contents of any w-bit memory word of a memory with n words, or ability to change this contents, is influenced by the contents of any other k-1 words of the memory. The proposed methodology uses a pseudo-exhaustive technique based on Reed-Solomon codes, which can be efficiently applied to a word-oriented RAMs, assuming small values of k. The methodology ensures the detection of any number of disjoint (not linked) k-coupling faults, whereby the involved k words may be located anywhere in the memory; i.e., no assumptions have to be made on the physical topology of the cells in the memory cell array because of the systematic structure of the proposed tests, they are well suited for BIST implementations.