Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Generation and application of pseudorandom sequences for random testing
Generation and application of pseudorandom sequences for random testing
Testing for Coupled Cells in Random-Access Memories
IEEE Transactions on Computers
Deterministic tests for detecting single V-coupling faults in RAMs
Journal of Electronic Testing: Theory and Applications
Exhaustive and Near-Exhaustive Memory Testing Techniques and theirBIST Implementations
Journal of Electronic Testing: Theory and Applications
Using March Tests to Test SRAMs
IEEE Design & Test
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
Fault Location Algorithms for Repairable Embedded
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Pseudo-exhaustive word-oriented DRAM testing
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Built-in Self Testing of Embedded Memories
IEEE Design & Test
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
IEEE Transactions on Computers
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The problem of exhaustive test generation for detection of coupling faults between cells in word-oriented memories is considered. According to this fault model, contents of any w-bit memory word in a memory with n words, or ability to change this contents, is influenced by the contents of any other s-1 words in the memory. A near optimal iterative method for construction of test patterns is proposed. The systematic structure of the proposed test results in simple BIST implementations.