Fault Diagnosis of RAMs from Random Testing Experiments
IEEE Transactions on Computers
Introduction to algorithms
Detection of coupling faults in RAMs
Journal of Electronic Testing: Theory and Applications
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
A model for sequential machine testing and diagnosis
Journal of Electronic Testing: Theory and Applications
An algebra of multiple faults in RAMs
Journal of Electronic Testing: Theory and Applications
A tight analysis of the greedy algorithm for set cover
Journal of Algorithms
March tests for word-oriented memories
Proceedings of the conference on Design, automation and test in Europe
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
A new framework for generating optimal March tests for memory arrays
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Generating March Tests Automatically
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
An Optimal Algorithm for the Automatic Generation of March Tests
Proceedings of the conference on Design, automation and test in Europe
Automatic Generation of Diagnostic March Tests
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
A data acquisition methodology for on-chip repair of embedded memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fault simulation and test algorithm generation for random access memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 14.98 |
A novel approach to automatic generation of diagnostic memory tests based on fault decomposition and output tracing is described. Fault decomposition allows fault models that precisely describe the fault effects of a specific technology to be considered during test generation; therefore, overtesting of the memory-under-test is avoided. Output tracing of failing memory cells allows for distinguishing of all memory faults of the fault model. An extended greedy-based set-cover algorithm is utilized to generate the march tests that detect all basic fault effects and distinguish among them. The effectiveness of the generated tests is verified using simulation. Test generation time is on the order of a few seconds, while the lengths of the generated tests are only 1N to 3N higher than those of known optimal tests for the same fault models.