Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
False write through and un-restored write electrical level fault models for SRAMs
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
18.2 Fault Models and Tests for Two-Port Memories
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Efficient Algorithms for Testing Semiconductor Random-Access Memories
IEEE Transactions on Computers
Generating march tests automatically
ITC'94 Proceedings of the 1994 international conference on Test
Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing
IEEE Transactions on Computers
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Given a set of memory array faults the problem ofcomputing an optimal march test that detects all specified memory array faults is addressed. In this paper, wepropose a novel approach in which every memory arrayfault is modeled by a set of primitive memory faults. Aprimitive march test is defined foreach primitive memory fault. We show that march tests that detect the specified memory array faults are composed of primitive marchtests. A method tocompute the optimal march tests forthe specified memory array faults is described. A set ofexamples to illustrate the approach is presented.