Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Testing complex couplings in multiport memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Consequences of port restrictions on testing two-port memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
March LR: a test for realistic linked faults
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Assessing SRAM test coverage for sub-micron CMOS technologies
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
18.2 Fault Models and Tests for Two-Port Memories
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Efficient Tests for Realistic Faults in Dual-Port SRAMs
IEEE Transactions on Computers
Self Test Architecture for Testing Complex Memory Structures
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs
Journal of Electronic Testing: Theory and Applications
DfT schemes for resistive open defects in RRAMs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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A two-port memory contains two similarports, which can be accessed separately and independent of each other. In this paper, logical fault modelsare derived for the effect of shorts between the ports.The result is a set of new fault models, based oncircuit simulation, together with a new test.